The present invention disclosed herein relates to a semiconductor memory device and more particularly, to a non-volatile semiconductor memory device and program method.
Demand has increased with respect to semiconductor memory devices that are electrically erased and programmed without needing of a refresh operation for retaining stored data. Further, the demand for semiconductor memory devices with large volume and high integration continues to increase. A NAND flash memory device may provide large volume and high integration without a refresh operation for keeping stored data. Since stored data is kept even at power-off, the NAND flash memory device is widely used by electronic apparatuses where a power is suddenly turned off.
FIG. 1 is a cross-sectional view of a conventional flash memory cell. Referring to FIG. 1, a flash memory cell 100 includes a source 120, a drain 130, a floating gate 140, and a control gate 150. The source and drain 120 and 130 are formed on a P-type semiconductor substrate 110 and are spaced apart by a channel region. The floating gate 140 is formed over the channel region with a thin insulation film interposed therebetween, and the control gate 150 is formed over the floating gate 140 with an insulation film interposed therebetween.
The source 120, the drain 130, the control gate 150 and the substrate 110 are connected with corresponding terminals Vs, Vd, Vg, and Vb, respectively, for receiving voltages required for program, erase, and read modes of operation. For example, during a program mode of operation, a program voltage (e.g., about 15V˜20V) is applied to a selected word line and a pass voltage (e.g., about 10V) lower than the program voltage is applied to unselected word lines, respectively.
In general, it is difficult to program a flash memory cell 100 via one program operation under the above-described voltage condition. The program operation may be ended when a threshold voltage of a programmed memory cell becomes sufficiently high by means of electron injection into its floating gate. After the program operation, a verify read operation is required to verify whether enough amount of charge is accumulated in a floating gate of a programmed memory cell to increase a threshold voltage of the programmed memory cell.
FIG. 2 is a flow diagram for describing a program operation of a conventional non-volatile memory device. Once a program mode of operation commences, at block 210, data to be programmed is loaded onto a page buffer circuit in a non-volatile memory device. At block 215, a loop count value indicating a loop number is reset to have a value of ‘0.’ At the next block 220, the loaded data in the page buffer circuit is programmed in a selected memory cell. An operation where data is programmed in a selected memory cell is well known to one skilled in the art, and description thereof is thus omitted.
At block 225, a verify read operation is carried out to judge whether the selected memory cell has a required/target threshold voltage. Data read out via the verify read operation may be stored in the page buffer circuit.
A control signal indicating a program pass or fail may be produced according to data stored in the page buffer circuit. In general, data stored in the page buffer circuit has a value complementary to the control signal. For example, in the case that data stored in the page buffer circuit is ‘0,’ the control signal has a value of logically ‘1.’ In the case that data stored in the page buffer circuit is ‘1,’ the control signal has a value of logically ‘0.’ Alternatively, it is possible to establish the data and the control signal so as to have the same value. Afterwards, the description will be made on the basis that data stored in the page buffer circuit has a value complementary to the control signal.
The control signal may be applied to a pass/fail check circuit (not shown) with a wired-OR structure. In accordance with the wired-OR structure, all control signals from the page buffer circuit may be provided as inputs of an OR gate.
At block 230, the pass/fail check circuit judges whether all control signals from the page buffer circuit have a program pass value (e.g., 0). If all control signals from the page buffer circuit are judged to have a program pass value, at block 235, a program operation is judged to be performed normally. Afterwards, the program mode of operation is ended.
If at least one control signal from the page buffer circuit has a program fail value (e.g., 1), that is, when the program operation is judged to be failed, then at block 240, it is judged whether a current loop number reaches a maximum loop number. If the current loop number reaches the maximum loop number, then at block 250, a program operation is judged to be performed abnormally. Afterwards, the program mode of operation is ended.
If the current loop number is lower than the maximum loop number, at block 245, the current loop number is increased by 1, and the procedure goes to block 220. Afterwards, the program operation is repeated in the above-described manner.
FIG. 3 is a diagram showing a case where a program operation results in a program pass. As illustrated in FIG. 3, data is loaded onto a page buffer. Next, a first loop is carried out. Each loop consists of a program operation (or, interval), a verify read operation (or, interval), and a pass/fail check operation (or, a judging operation/interval). A program operation is repeated until it is judged to result in a program pass, with a loop number being increased for each repetition. In the case that a program operation is judged to be passed at a pass/fail check operation of a kth loop (i.e., at Loop k of FIG. 3) the program mode of operation is ended as a program pass.
FIG. 4 is a diagram showing a case where a program operation results in a program failed. As illustrated in FIG. 4, data is loaded onto a page buffer circuit. Next, a first loop is carried out. Each loop consists of a program operation, a verify read operation, and a pass/fail check operation. A program operation is repeated until it is judged to result in a program fail, with a loop number being increased for each repetition. In the case that a program operation is judged to be failed at a pass/fail check operation of a maximum loop (i.e., Loop Max of FIG. 4), the program mode of operation is ended as a program fail.
A certain amount of time is taken for a pass/fail check operation of a conventional non-volatile memory device. For example, about several microseconds are taken to perform a pass/fail check operation once. As a result, the pass/fail check operation causes performance limitations such that it impedes improvement to a program speed.